1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to an apparatus for energy recovery of a plasma display panel.
2. Description of the Background Art
Generally, a plasma display panel (hereinafter abbreviated PDP) consisting of a plurality of matrix type cells displays an image by turning on/off discharge cells in a manner of bringing about high-voltage discharges in the cells, respectively. However, the discharge characteristic of PDP needs power consumption relatively greater than that of other display devices. In order to reduce the power consumption, unnecessary power consumption occurring in the course of a driving process without direct relation to discharge needs to be minimized as well as luminous efficiency is raised.
An AC type PDP utilizes surface discharge occurring on a surface of a dielectric coated on electrodes. In the AC type PDP, a drive pulse for sustain discharge of tens of thousands to several millions cells is a high voltage ranging from several tens volts to several hundreds volts and its frequency exceeds several hundreds KHz. When the drive pulse of high voltage is applied to the cell, an electric charging/discharge of high capacitance takes place.
In case that the electric charging/discharge occurs in PDP, a capacitance load of a panel causes no energy consumption. Yet, since the drive pulse is generated from the switching of DC power, considerable energy loss is brought about in PDP. Specifically, if an excessive current flows within a cell on discharge, the energy loss increases. The energy loss triggers a temperature rise of switching devices to break down the switching devices of a drive circuit in the worst case. In order to recover the energy unnecessarily occurring within the panel, the drive circuit of PDP includes an energy recovery circuit.
FIG. 1 is a diagram of an energy recovery circuit according to a related art.
Referring to FIG. 1, an energy recovery circuit comprises first and second switches S1 and S2 connected parallel between an inductor L and an external capacitor Css, a third switch S3 for supplying a sustain voltage Vs to a panel capacitor Cp, and a fourth switch S4 for supplying a ground voltage GND to the panel capacitor Cp. And, first and second diodes D1 and D2 are connected between the first and second switches S1 and S2 to put limitation on a reverse current.
The panel capacitor Cp equivalently indicates a capacitance value of the panel, and reference numbers Re and R_Cp equivalently represent parasitic resistances of an electrode provided to the panel and the corresponding cell, respectively. The first to fourth switches S1, S2, S3, S4 are implemented by semiconductor switch devices such as MOSFET devices, respectively.
Assuming that the external capacitor Css is charged with a voltage of Vs/2, an operation of the energy recovery circuit shown in FIG. 1 is explained with reference to FIG. 2 as follows. In FIG. 2, Vp indicates a voltage of the panel capacitor Cp and IL indicates a current of the inductor L.
First of all, the first switch S1 is turned on and maintains a turned-on state during an ER-UP period. During the ER-UP period, the second to fourth switches S2 to S4 maintain a turned-off state. If so, the voltage stored in the external capacitor Css is supplied to the inductor L via the first switch S1 and the first diode D1. The inductor L constructs a serial LC resonance circuit together with the panel capacitor Cp, whereby the panel capacitor Cp starts to be charged with a resonance waveform. During the ER-UP period, the current IL of the inductor L is discharged to zero after having been charged with a positive peak by electric charges from the external capacitor Css and the voltage Vp of the panel capacitor Cp is charged up to the sustain voltage Vs as a maximum potential.
If the current of the inductor L becomes zero, the third switch S3 is turned on to maintain the turned-on state during a first clamping period. During the first clamping period, the first switch S1 maintains the turned-on state but the second and fourth switches S2 and S4 maintain the turned-off state. During the first clamping period, the sustain voltage Vs is supplied to the panel capacitor Cp via the third switch S3. Hence, the voltage Vp of the panel capacitor Cp is constantly maintained at the sustain potential Vs. The current IL of the inductor L maintains zero during the first clamping period. Thus, plasma discharge occurs between both ends of the panel capacitor Cp within the cell while the voltage Vp is of the panel capacitor Cp is constantly maintained.
After expiration of the first clamping period, the second switch S2 is turned on to maintain a turned-on state during an ER down (hereinafter abbreviated ER-DN) period. During the ER-DN period, the third switch S3 is turned off but the first and fourth switches S1 and S4 maintain turned-off states, respectively. If so, a null power failing to contribute to the plasma discharge is recovered to the external capacitor Css from the panel capacitor Cp via the inductor L, second diode D2, and second switch S2. During the ER-DN period, the current IL of the inductor L is discharged to zero after having been charged up to a negative peak by electric charges from the panel capacitor Cp and the voltage Vp of the panel capacitor Cp is discharged down to the ground potential GND from the sustain potential Vs.
If the current of the inductor L becomes zero at the time point of expiration of the ER-DN period, the fourth switch S4 is turned on to maintain a turned-on state during a second clamping period. And, the second switch S2 is turned off but the first and third switches S1 and S3 maintain turned-off states, respectively during the second clamping period. The ground voltage GND is supplied to the panel capacitor Cp via the fourth switch S4 during the second clamping period. Hence, the voltage Vp of the panel capacitor Cp is constantly maintained at the ground potential GND.
However, in the related art energy recovery circuit, the time required for charging the panel capacitor Cp up to the sustain voltage Vs, i.e. the ER-UP period, becomes elongated excessively. Hence, it is difficult to apply the related art recovery circuit to the high-resolution PDP. Moreover, if the voltage Vp of the panel capacitor Cp smoothly increases, the timing point that the plasma discharge occurs within the cell is elongated to make the plasma discharge unstable. Hence, a width of the drive pulse needs to be increased to implement the stabilization of the plasma discharge.